1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to silicon nitride based sidewall spacers exhibiting improved reliability during transistor fabrication, and to a method for forming a transistor using these spacers.
2. Description of the Related Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. Typically, a gate dielectric is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and a drain. Dielectric spacers are often formed on the sidewalls of the gate conductor and used to form lightly-doped drain (LDD) portions of the source and drain. According to the conventional method of forming these LDD regions, the above-mentioned dopant impurities are introduced in two steps. A first impurity introduction is performed after gate conductor formation to form impurity distributions self-aligned to sidewalls of the gate conductor. A conformal dielectric layer, typically a silicon dioxide ("oxide") layer is subsequently blanket deposited over the semiconductor substrate and gate conductor. This oxide layer is anisotropically etched more rapidly in a vertical than a horizontal direction, so that oxide spacers are formed adjacent to the gate conductor sidewalls. A second impurity introduction is subsequently performed to form impurity distributions self aligned to lateral surfaces of the spacers. The impurity distributions formed by the second impurity introduction have higher carrier concentration and extend farther into the substrate than those formed by the first impurity introduction.
The impurity distributions formed by the first and second impurity introductions combine to form source and drain regions which include relatively shallow and lightly-doped portions, or LDD regions, underneath the sidewall spacers. Such LDD regions reduce the maximum electric field at the drain/channel interface in a MOSFET. The reduction in electric field lowers the kinetic energy gained by electrons in the MOSFET channel, thereby mitigating undesirable "hot-carrier" effects. Hot-carrier effects include avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric.
In addition to their use in forming LDD regions, sidewall spacers are useful in forming a self-aligned silicide, or salicide, subsequent to source and drain formation. Salicides are formed in order to provide relatively broad-area, low-resistivity (and therefore low-resistance) contacts to the source, drain, and gate of a transistor. In a salicide process, a metal film is blanket-deposited over the exposed surfaces of a transistor containing sidewall spacers, after formation of the source and drain regions. The transistor is subjected to a heating process which causes a reaction between the metal and silicon that the metal is in contact with, forming a silicide on the silicon surfaces. Unreacted metal, such as that deposited over the sidewall spacers, is subsequently removed, leaving the silicide covering only the gate, source, and drain regions.
Despite the above-described benefits of sidewall spacer formation, there are reliability problems associated with sidewall spacers. As noted above, spacers are typically formed from a deposited oxide layer. Such oxide spacers are susceptible to attack by the hydrofluoric acid (HF) based etches typically used to clean native oxides from the gate, source and drain surfaces prior to the salicide process metal deposition. In addition, some of the dopant impurities used in transistor fabrication diffuse readily through oxide. In particular, boron is known to exhibit significant outdiffusion from silicon into overlying oxide layers during MOSFET fabrication. In a p-channel transistor, for example, boron may diffuse from the p-type source and drain into oxide sidewall spacers. This outdiffusion of boron from the substrate lowers the carrier concentration of the source and drain regions, thereby increasing series and contact resistances associated with the source and drain.
Another reliability problem which may be associated with oxide spacers is "bridging" over spacers during self-aligned silicide, or salicide, processes. Bridging occurs when silicon atoms which are not bonded into the spacer insulator are present on the surface of the spacer, so that a silicide is formed over the spacers. This silicide remains when unreacted metal is removed, so that silicide bridging from the gate to source or drain regions may occur. Silicon atoms which cause bridging may diffuse from the gate, source and/or drain regions into the metal overlying the sidewall spacers, so that a silicide is formed. Titanium is a popular silicide metal because it has a very low resistance. Unfortunately, titanium salicide processes are particularly prone to bridging.
A promising approach to the reliability problems described above is to use silicon nitride ("nitride"), rather than oxide, for spacer formation. First of all, nitride is not susceptible to attack by the HF-based etches used to remove native oxides. Nitride is also believed to be more resistant to dopant diffusion than oxide. Spacers formed with nitride may therefore limit outdiffusion of impurities from the gate and/or source/drain regions. This diffusion limiting capability may be especially significant in the case of p-channel transistors, which are typically implanted with boron. As noted above, boron is known to exhibit significant outdiffusion from silicon into adjacent oxide layers during MOSFET fabrication. Furthermore, the presence of nitrogen in a sidewall spacer is believed to limit the bridging, described above, which can occur during salicide formation. Using a nitrogen ambient during the titanium silicide reaction process is known to prevent bridging during titanium salicide processes. The presence of nitrogen is believed to lower the diffusivity of silicon in titanium. Formation of a nitride spacer may therefore provide a source of nitrogen to reduce bridging across the spacer.
Although nitride spacers may alleviate some spacer reliability problems, as discussed above, other reliability problems can result from their use. For example, pre-amorphization implants often used prior to salicide formation may cause dissociation of the surface region of nitride spacers, as discussed further below.
Many modern transistor fabrication processes involve short (less than 1 micron long) polysilicon gate conductors. When silicides are formed on upper surfaces of these gate conductors, the resulting gate structure is termed a "polycide" structure. These polycide gate conductors have been found to exhibit geometry-dependent resistivity, with shorter-length gate conductors having higher resistivity. It has been theorized that regions of high resistivity polysilicon, in which mobile carriers become easily trapped, exist in the vicinity of the grain boundaries characteristic of polysilicon films. As these regions become comparable in size to the overall length of the polysilicon gate conductor, insufficient quantities of silicon may be available for the formation of high quality silicides. When such a condition occurs, the formation rate and quality of silicides formed on the upper surface of short-length polysilicon gate conductors may drop below the formation rate and quality of silicides formed on wider polysilicon structures. The increased resistivity exhibited by short-length gate conductor polycides results in an increased gate contact resistance, which reduces the speed of the transistor. Furthermore, geometry-dependent silicide resistivity is undesirable because semiconductor devices and process are almost universally designed and simulated under the assumption that silicide resistivity will not exhibit a geometric dependence.
An approach which has been found useful in reducing the resistivity of short polysilicon gate conductor silicides is the use of an amorphizing implant prior to metal deposition. In such a pre-amorphization implant, non-dopant atoms such as Si or Ge are typically implanted into upper surface regions of the polysilicon gate conductor, the source and drain regions, and the sidewall spacers. This implant is believed to break up the grain boundaries in the upper surface portion of the polysilicon gate conductor, such that a lower-resistivity silicide layer may subsequently be formed. Unfortunately, such an implant tends to dissociate silicon nitride, resulting in unbound Si atoms on the surface of nitride spacers. These Si atoms may subsequently react with a deposited metal, forming silicide over the nitride spacers. It is postulated that the bond recombination energies associated with nitride and oxide are such that silicon from dissociated nitride is more likely to form a silicide when heated with a metal during a salicide process than to re-form nitride. Silicon from dissociated oxide, on the other hand, is believed to be more likely to re-form oxide during a salicide process. In this way, the silicide bridging described above may occur if dissociated nitride is present on the nitride spacers.
It would therefore be desirable to develop nitride-based sidewall spacers which are resistant to dissociation by pre-amorphization implants. The desired spacers should minimize reliability problems associated with many typical oxide spacers, such as dopant diffusion and salicide bridging.